1. Field of the Invention
The present invention relates to data processing system equipped with an instruction prefetch device.
2. Description of the Prior Art
FIG. 4 shows the instruction prefetch section of a conventional data processing system or computer having a plurality of types of instructions and an instruction prefetch queue. It consists of a main memory 1, an instruction prefetch queue 2, a processing section 3 for processing the instruction base portion, a processing section 4 for processing the instruction extension portion, a pointer PI for instruction prefetch queue input, and a pointer PO for instruction prefetch queue output.
The operation will be described with reference to FIG. 5. Suppose that instruction types include a type 1 consisting of an operation code (one word length) and a literal (one word length) and a type 2 consisting of only an operation code (one word length). The word herein used has an appropriate length for expressing an operation code and a literal code. The literal code means displacement value, immediate value, absolute value (address), etc. The operation code and literal code are processed in the processing sections 3 and 4, respectively. The process is carried out in phases. The phase herein used means the time required to fetch one word from the instruction prefetch queue 2 or advance the pointer. In order to make the description clearer, respective phases will be given numbers, such as PH 1, PH 2, . . . . The same reference numerals or characters denote identical parts or equivalents in the drawings throughout the description.
In the PH 1, a word of an instruction is fetched into the processing section 3. In the PH 2, the fetched instruction is analyzed and the pointer PO's value is incremented by one. In the PH 2, the type of the fetched instruction is also determined. If it is a type 1, one word is fetched to the processing section 4 in the PH 3. While the processor 4 processes it, the pointer PO's value is simultaneously incremented by one in the PH 4. In the PH 5, a word of another instruction is fetched to the processing section 3. In the PH 6, the fetched instruction is analyzed while the pointer PO's value is incremented by one. If the instruction is determined to be a type 2, a word of another instruction is fetched to the processing section 3 instead of the processing section 4 in the PH 7. In this way, the types 1 and 2 of instructions are processed.
As has been described above, in the conventional computer equipped with an instruction prefetch queue, either the processing section 3 or processing section 4 can operate at a time, thus requiring four phases to process a type-1 instruction and two phases to process a type-2 instruction and has poor processing efficiency.